1. Field of the Invention
The present invention relates to an A/D conversion circuit that converts an analog signal into digital data and a solid-state imaging device having the A/D conversion circuit.
The application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2012-284604, filed Dec. 27, 2012, the entire contents of which are incorporated herein.
2. Background Art
As an example of an A/D conversion circuit used in a solid-state imaging device according to the related art, a configuration illustrated in FIG. 14 has been known (for example, Japanese Unexamined Patent Application, First Publication No. 2012-039386). Firstly, the configuration and the operation of the A/D conversion circuit illustrated in FIG. 14 will be described. The A/D conversion circuit illustrated in FIG. 14 includes a comparison unit 11, a signal generation unit 12, a latch unit 13, a counter 14, and a delay unit 15.
The delay unit 15 includes a plurality of delay units DU[0] to DU[7] that delay and output an input signal. A start pulse Start_P is input to the first delay unit DU[0]. The comparison unit 11 includes a voltage comparator COMP that receives an analog signal Sig, which is an object of time detection, and a ramp wave Ramp that decreases with the lapse of time, and outputs an output signal CO indicating a result obtained by comparing the analog signal Sig with a signal voltage of the ramp wave Ramp. In the comparison unit 11, a time interval (a size in the time axis direction) corresponding to the amplitude of the analog signal Sig is generated.
The signal generation unit 12 includes an inversion delay circuit DLY that inverts and delays the output signal CO, and an AND circuit AND1 that outputs an output signal Hold_L obtained by performing an AND operation on the output signal CO and an output signal xCO_D of the inversion delay circuit DLY. The latch unit 13 includes latch circuits D_0 to D_7 that latch the logic states of output signals CK0 to CK7 of the delay units DU[0] to DU[7] of the delay unit 15. Furthermore, the latch unit 13 includes an AND circuit AND2 that outputs an output signal Hold_C, which is obtained by performing an AND operation on the output signal xCO_D of the inversion delay circuit DLY of the signal generation unit 12 and a control signal Enable1, to the latch circuit DU[7]. The counter 14 includes a counter circuit CNT that performs counting based on the output signal CK7 that is input from the delay unit 15 through the latch circuit D_7.
The latch circuits D_0 to D_6 changes to an enable (valid) state when the output signal Hold_L is in a High state (a logic value “1”), and output the output signals CK0 to CK6 of the delay units DU[0] to DU[6]. Furthermore, the latch circuits D_0 to D_6 changes to a disable (invalid) state when the output signal Hold_L is in a Low state (a logic value “0”), and latch logic states corresponding to the output signals CK0 to CK6 of the delay units DU[0] to DU[6].
The latch circuit D_7 changes to the enable (valid) state when the output signal Hold_C is in the High state, and outputs the output signal CK7 of the delay unit DU[7]. Furthermore, the latch circuit D_7 changes to the disable (invalid) state when the output signal Hold_C is in the Low state, and latches a logic state corresponding to the output signal CK7 of the delay unit DU[7].
A counter latch circuit that latches the logic state of a counting result of the counter 14 is not illustrated. However, a counter circuit having a latch function is used, so that the counter 14 is also used as the counter latch circuit.
Next, an operation of the related art will be described. FIG. 15 illustrates the operation of the A/D conversion circuit according to the related art.
FIG. 15 illustrates waveforms of the ramp wave Ramp, the analog signal Sig, the start pulse Start_P, the output signals CK0 to CK7 of the delay units DU[0] to DU[7], the output signal CO of the comparison unit 11, the output signal xCO_D of the inversion delay circuit DLY, the output signal Hold_L of the AND circuit AND1, the control signal Enable1, the output signal Hold_C of the AND circuit AND2, and the signals Q0 to Q7 output from the latch circuits D_0 to D_7 from the top. In FIG. 15, the vertical direction indicates signal voltage and the horizontal direction indicates time.
Firstly, at a timing (a first timing) according to the comparison start of the comparison unit 11, a clock of a cycle approximately coinciding with a delay time (the sum of delay times of the eight delay units DU[0] to DU[7]) of the delay unit 15 is input to the delay unit 15 as the start pulse Start_P. In this way, the delay unit 15 starts to operate. The delay unit DU[0] constituting the delay unit 15 delays the start pulse Start_P and outputs the output signal CK0, and the delay units DU[1] to DU[7] constituting the delay unit 15 delay output signals of delay units of a previous stage and output the output signals CK1 to CK7. The output signals CK0 to CK7 of the delay units DU[0] to DU[7] are input to the latch circuits D_0 to D_7 of the latch unit 13. At this time, since the output signal CO of the comparison unit 11 is in the Low state and the output signal xCO_D of the inversion delay circuit DLY is in the High state, the output signal Hold_L of the AND circuit AND1 of the signal generation unit 12 changes to the Low state and the latch circuits D_0 to D_6 are in the disable state, so that the A/D conversion circuit stops operating.
Meanwhile, since the output signal xCO_D of the inversion delay circuit DLY is in the High state and the control signal Enable1 is in the High state, the output signal Hold_C of the AND circuit AND2 of the latch unit 13 changes to the High state, so that the latch circuit D_7 changes to the enable state and outputs the input output signal CK7 of the delay unit DU[7] to the counter 14 as is.
The counter 14 performs a counting operation based on the output signal CK7 of the delay unit DU[7], which is output from the latch circuit D_7 of the latch unit 13. In the counting operation, a count value increases or decreases with the rise or the fall of the output signal CK7.
At a timing (a second timing) at which the analog signal Sig approximately coincides with the signal voltage of the ramp wave Ramp, since the output signal CO of the comparison unit 11 is inverted, the output signal Hold_L of the AND circuit AND1 of the signal generation unit 12 changes to the High state. In this way, the latch circuits D_0 to D_6 change to the enable state. After the lapse of a time coinciding with a delay time of the inversion delay circuit DLY of the signal generation unit 12 from the second timing (at a third timing), since the output signal xCO_D of the inversion delay circuit DLY of the signal generation unit 12 is inverted, the output signal Hold_L of the AND circuit AND1 of the signal generation unit 12 changes to the Low state. In this way, the latch circuits D_0 to D_6 change to the disable state. At this time, the logic states corresponding to the output signals CK0 to CK6 of the delay units DU[0] to DU[6] are latched by the latch circuits D_0 to D_6 . Furthermore, since the output signal Hold_C of the AND circuit AND2 of the latch unit 13 changes to the Low state at the third timing, the latch circuit D_7 changes to the disable state and the logic state corresponding to the output signal CK7 of the delay unit DU[7] is latched by the latch circuit D_7. In the case of FIG. 15, the logic states of the signals latched by the latch circuits D_0 to D_7 are (11100001)2=(D_7=1, D_6=1, D_5=1, D_4=0, D_3=0, D_2=0, D_1=0, and D_0=1) (“0” corresponds to a Low state and “1” corresponds to a High state). In the present specification, (*)2 (* is a sequence of 0 and 1) indicates a binary number.
The counter 14 latches a count value when the latch circuit D_7 stops operating. By the logical state latched in the latch unit 13 and the count value latched in the counter 14, digital data corresponding to the analog signal Sig is obtained.
In accordance with the A/D conversion circuit according to the related art, since the latch circuits D_0 to D_6 operate only during a period from the second timing to the third timing, it is possible to reduce current consumption of the latch unit, resulting in the reduction of current consumption of the A/D conversion circuit.
FIG. 16 illustrates an example of the configuration of the latch circuits D_0 to D_7 provided in the latch unit 13. As illustrated in FIG. 16, each of the latch circuits D_0 to D_7 includes a NAND circuit NAND1, inversion circuits NOT1 and NOT2, and a switch circuit SW. The switch circuit SW further includes switch circuits L_SW1 and L_SW2.
One input terminal (a first input terminal) of the NAND circuit NAND1 is connected to an input terminal D. The other input terminal of the NAND circuit NAND1 is connected to an input terminal SET (a second input terminal). One end of the switch circuit L_SW1 is connected to an output terminal of the NAND circuit NAND1. The other end of the switch circuit L_SW1 is connected to an input terminal of the inversion circuit NOT1 and one end of the switch circuit L_SW2. An input terminal of the inversion circuit NOT2 is connected to an output terminal of the inversion circuit NOT1. The other end of the switch circuit L_SW2 is connected to an output terminal of the inversion circuit NOT2 and an output terminal Q.
When an input signal of the input terminal SET of each of the latch circuits D_0 to D_7 is in the Low state, since an output signal of the NAND circuit NAND1 changes to the High state regardless of the logic state of an input signal of the input terminal D, the latch circuits D_0 to D_7 change to the disable state. Furthermore, when the input signal of the input terminal SET of each of the latch circuits D_0 to D_7 is in the High state, since the NAND circuit NAND1 inverts and outputs the logic state of the input signal of the input terminal D, the latch circuits D_0 to D_7 change to the enable state.
A control terminal CK′ of the switch circuits L_SW1 and L_SW2 is connected to an input terminal CK, and the switch circuits L_SW1 and L_SW2 are controlled by an input signal of the input terminal CK. The switch circuit L_SW1 is turned ON when the input signal of the input terminal CK is in the High state, and is turned OFF when the input signal of the input terminal CK is in the Low state. The switch circuit L_SW2 is turned ON when the input signal of the input terminal CK is in the Low state, and is turned OFF when the input signal of the input terminal CK is in the High state.
The output signal Hold_L of the AND circuit AND1 is input to the input terminals CK and SET of the latch circuits D_0 to D_6 , and the output signals CK0 to CK6 of the delay units DU[0] to DU[6] are input to the input terminals D of the latch circuits D_0 to D_6 . Meanwhile, the output signal Hold_C of the AND circuit AND2 is input to the input terminal CK of the latch circuits D_7, and a power supply voltage is input to the input terminal SET of the latch circuits D_7. The output signal CK7 of the delay units DU[7] is input to the input terminal D of the latch circuits D_7.
FIG. 17 illustrates the operation of the latch circuits D_0 to D_6 when the latch circuits D_0 to D_6 are in an ideal state in which there is no reduction of a power supply voltage and no increase in a ground voltage, and FIG. 18 illustrates the operation of the latch circuits D_0 to D_6 when the reduction of the power supply voltage and the increase in the ground voltage occur in the latch circuits D_0 to D_6 . FIG. 17 and FIG. 18 illustrate the waveforms of the input signals of the input terminals CK, SET, and D of each of the latch circuits D_0 to D_6 , the output signal of the NAND circuit NAND1, and the output signal of the output terminal Q from the top. In FIG. 17 and FIG. 18, the vertical direction indicates a signal voltage and the horizontal direction indicates a time. VDD indicates the power supply voltage and GND indicates the ground voltage.
When the power supply voltage and the ground voltage of the latch circuits D_0 to D_6 are in an ideal state, the NAND circuit NAND1 inverts and outputs the logic state of the input signal of the input terminal D immediately at the timing at which the input signal (the output signal Hold_L of the AND circuit AND1) of the input terminals CK and SET changes from the Low state to the High state, and the latch circuits D_0 to D_6 change to the enable state, as illustrated in FIG. 17. Then, the latch circuits D_0 to D_6 hold a signal (the Low state in FIG. 17) obtained by inverting the input signal D at the timing at which the input signal (the output signal Hold_L of the AND circuit AND1) of the input terminals CK and SET change from the High state to the Low state.
However, when the reduction of the power supply voltage and the increase in the ground voltage occur in the latch circuits D_0 to D_6 , since the operation of each circuit constituting the latch circuits D_0 to D_6 is delayed, the NAND circuit NAND1 may not be able to invert and output the logic state of the input signal of the input terminal D immediately at the timing at which the input signal (the output signal Hold_L of the signal generation unit 12) of the input terminal SET changes from the Low state to the High state, as illustrated in FIG. 18. In this case, also at the timing at which the input signal (the output signal Hold_L of the AND circuit AND1) of the input terminal CK changes from the High state to the Low state, since the output signal of the NAND circuit NAND1 does not change to the Low state, the latch circuits D_0 to D_6 may hold a signal (the High state in FIG. 18) equal to the input signal D.
As one method for performing encoding (binarization) of the logic states latched in the latch circuits D_0 to D_7, there is a method for outputting an encoded value, which corresponds to a position at which the logic states of signals latched in the latch circuits D_0 to D_7 are switched from 0 to 1 (or from 1 to 0), when the logic states of the signals are viewed in the same direction in an arrangement order of the latch circuits D_0 to D_7. In the operation illustrated in FIG. 15, when the aforementioned abnormal operation does not occur in the latch circuit D_6 of the AD conversion circuit, the logic states of the signals latched in the latch circuits D_0 to D_7 are (11100001)2=(D_7=1, D_6=1, D_5=1, D_4=0, D_3=0, D_2=0, D_1=0, and D_0=1) (“0” corresponds to the Low state and “1” corresponds to the High state) as described above. In this case, since there is only one position at which the logic states of the signals latched in the latch circuits D_0 to D_7 are switched from 0 to 1, encoding is correctly performed.
Meanwhile, in the operation illustrated in FIG. 15, when the aforementioned abnormal operation occurs in the latch circuit D_6 of the AD conversion circuit, the logic states of the signals latched in the latch circuits D_0 to D_7 are (10100001)2=(D_7=1, D_6=0, D_5=1, D_4=0, D_3=0, D_2=0, D_1=0, and D_0=1) (“0” corresponds to the Low state and “1” corresponds to the High state). In this case, when encoding is performed using the aforementioned method, there are two positions at which the logic states of the signals latched in the latch circuits D_0 to D_7 are switched from 0 to 1. As described above, when there are two positions at which the logic states of the signals latched in the latch circuits D_0 to D_7 are switched from 0 to 1, it causes incorrect encoding, resulting in a possibility of an error of 1 LSB or more occurring.